This invention relates generally to FLASH memory and methods of forming FLASH memory.
Memory is but one type of integrated circuitry. Some memory circuitry allows for both on-demand data storage and data retrieval. For example, memories which allow both writing and reading, and whose memory cells can be accessed in a random order independent of physical location, are referred to as random-access memories (RAM). Read-only memories (ROMs) are those in which only the read operation can be performed rapidly. Entering data into a read-only memory is typically referred to as programming, and the operation is considerably slower than the writing operation utilized in random-access memory. With random-access memory, information is typically stored with respect to each memory cell either through charging of a capacitor or the setting of a state of a bi-stable flip-flop circuit. With either, the stored information is destroyed when power is interrupted. Read-only memories are typically non-volatile, with the data being entered during manufacturing or subsequently during programming.
Some read-only memory devices can be erased as well as written to by a programmer. Erasable read-only memory typically depends on the long-term retention of electronic charge as the information storage mechanism. The charge is typically stored on a floating semiconductive gate, such as polysilicon. One type of read-only memory comprises FLASH memory. Such memory can be selectively erased rapidly through the use of an electrical erase signal.
A FLASH memory cell typically comprises a single floating gate transistor. For multiple storage cells, such as used in large semiconductor memories, the storage cells of the memory are arranged in an array consisting of rows and columns. The rows are typically considered as comprising individual conductive gate lines formed as a series of spaced floating gates received along a single conductive line (hereafter referred to as xe2x80x9ca line of floating gatesxe2x80x9d). Source and drain regions of the cells are formed relative to active area of a semiconductor substrate, with the active areas being generally formed in lines running substantially perpendicular to the lines of floating gates. The sources and drains are formed on opposing sides of the lines of floating gates within the active area with respect to each floating gate of the array. Thus, lines (rows) of programmable transistors are formed.
Electrical connections are made with respect to each drain to enable separate accessing of each memory cell. Such interconnections are arranged in lines comprising the columns of the array. The sources in FLASH memory, however, are typically all interconnected and provided at one potential, for example ground, throughout the array. Accordingly, the source regions along a given line of floating gates are typically all provided to interconnect within the substrate in a line running parallel and immediately adjacent the line of floating gates. These regions of continuously running source area are interconnected outside of the array, and strapped to a suitable connection for providing the desired potential relative to all the sources within the array. Accordingly, prior art techniques have been utilized to form a line of continuously running implanted source material within the semiconductor substrate and running parallel with the floating gate word lines.
In a principal technique of achieving the same, the substrate has first been fabricated to form field oxide regions by LOCOS. The fabrication forms alternating strips of active area and LOCOS field oxide running substantially perpendicular to the floating gate word lines which will be subsequently formed. Thus running immediately adjacent and parallel with the respective word lines will be an alternating series of LOCOS isolation regions and active area regions on both the source and drain sides of a respective line of floating gates. After forming the lines of floating gates and to provide a continuous line of essentially interconnected source regions, the substrate is masked to form an exposed area on the source side of the respective lines of floating gates. The LOCOS oxide is then selectively etched relative to the underlying substrate. This leaves a series of spaced trenches along the lines of floating gates the result of removal of oxide from the previously oxidized substrate which formed the LOCOS regions.
Non-recessed LOCOS in fabrication of FLASH memory in this manner is typically very shallow relative to the semiconductor substrate (i.e., less than 1500 Angstroms deep). This leaves a gradual, almost sinusoidal, undulating surface of exposed semiconductor substrate running in lines substantially parallel and immediately adjacent the lines of floating gates on the desired source side. With the gently sloping sidewalls of the trenches or recesses left by the LOCOS oxide removal, one or more source ion implant steps are conducted through the mask openings of the remaining photoresist layer. The result is formation of a continuously and conductively doped source line within the semiconductor substrate immediately adjacent the line of floating gates.
Circuitry fabrication and isolation of adjacent circuitry within a semiconductor substrate can also be achieved with a trench isolation that is different from LOCOS. For example, trenches can initially be etched within a semiconductor substrate and subsequently filled with an insulating material, such as high density plasma deposited oxide. Such trenches can and are sometimes made considerably deeper relative to the outer substrate surface as compared to the oxidation depth of LOCOS. Accordingly, the etching typically produces elongated, deeper and straighter sidewalls than LOCOS. Regardless of whether using LOCOS or trench isolation, the etching away of the isolation regions (typically undoped silicon dioxide) to ultimately form continuous source lines typically attacks both the insulated top of the floating gate line stack and the active area source regions thereadjacent. Presently using an etching gas chemistry mixture of CF4, CHF3 and argon, it has been discovered that selectivity to silicon in forming the continuous silicon source area is not as great as desired, with in many instances 600 Angstroms of silicon being etched in the active/non-isolation area.
Such silicon loss has previously been considered to be insignificant. Yet recent consideration has shown that such silicon loss can have a detrimental effect on FLASH cell reliability and erase uniformity. It would be desirable to develop improved FLASH cell memory fabrication processes which reduce such silicon loss.
The invention includes methods of forming FLASH memory. In one implementation, a method of forming a line of FLASH memory cells includes forming a first line of floating gates over a crystalline silicon comprising semiconductor substrate. An alternating series of SiO2 comprising isolation regions and active areas are provided in the semiconductor substrate in a second line adjacent and along at least a portion of the first line of floating gates. The series of active areas define discrete transistor source areas separated by isolation regions. A masking layer is formed over the floating gates, the regions and the areas. A third line mask opening is formed in the masking layer over at least a portion of the second line. Substantially anisotropic etching is conducted of the SiO2 comprising isolation regions exposed through the third line mask opening substantially selectively relative to crystalline silicon exposed through the third line mask opening using a gas chemistry comprising a combination of at least one non-hydrogen containing fluorocarbon having at least three carbon atoms and at least one hydrogen containing fluorocarbon. The isolation regions are preferably formed in trenches previously etched into the crystalline silicon comprising semiconductor substrate. The substantially anisotropic etching preferably removes substantially all of the third line opening exposed isolation regions. Further, conductivity enhancing impurity is preferably implanted through the third line opening into the crystalline silicon comprising semiconductor substrate beneath the trenches, along sidewalls of the trenches and between the trenches and forming therefrom a continuous line of source active area within the crystalline silicon comprising semiconductor substrate along at least a portion of the first line of floating gates.